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Instruction set architecture
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241	Deploying LTTng on Exotic Embedded Architectures Mathieu Desnoyers École Polytechnique de Montréal Michel R. Dagenais École Polytechnique de Montréal Add to Reading List Source URL: lttng.org Language: English - Date: 2009-04-28 00:51:18 Debuggers Instruction set architectures Beta software LTTng Tracing High Precision Event Timer Linux kernel Embedded system 64-bit Computer architecture Software Computing
242	_ V9Technical Notes Add to Reading List Source URL: www.isystem.com Language: English - Date: 2015-05-27 07:21:02 IEEE standards Embedded systems Electronics manufacturing Joint Test Action Group Microcontrollers Instruction set architectures ARM architecture X86 debug register Nexus Electronics Computing Computer architecture
243	Freedom CPU Project F-CPU Design Team Draft and Request For Comment F-CPU MANUAL REV. 0.2.7c Add to Reading List Source URL: f-cpu.seul.org Language: English - Date: 2002-11-16 10:50:45 Instruction set architectures Central processing unit DEC Alpha CPU design Microprocessor Reduced instruction set computing Computer architecture Computer hardware Electronic engineering
244	BASIC Tiger® Module E Copyright © by Wilke Technology GmbH Krefelder Str. 147 Add to Reading List Source URL: www.jedmicro.com.au Language: English - Date: 2009-03-09 09:32:15 Computer architecture Out-of-band management Serial port Tiger-BASIC Electronics Instruction set architectures Microcontrollers Embedded systems Computing
245	Automatic Generation of Compact Programs and Virtual Machines for Scheme Mario Latendresse Department of Computer Science Rice University Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:05:10 Programming language implementation Macro Machine code Stack machine Instruction set ARM architecture Tail call Bytecode Programming language Computing Software engineering Computer programming
246	METAMOC: MODULAR EXECUTION TIME ANALYSIS USING MODEL CHECKING Andreas E. Dalsgaard1, Mads Chr. Olesen1, Martin Toft1, Ren´e R. Hansen1, Kim G. Larsen1 Abstract Safe and tight worst-case execution times (WCETs) are impor Add to Reading List Source URL: people.cs.aau.dk Language: English - Date: 2012-10-25 20:25:12 Central processing unit Instruction set architectures Classes of computers CPU cache Computer memory Worst-case execution time ARM9 Cache Microarchitecture Computer architecture Computing Computer hardware
247	16-BIT V SERIESTMAND 16-BIT MICROPROCESSORS INSTRUCTION V20TM, V30TM Add to Reading List Source URL: www.buchty.net Language: English - Date: 2013-11-07 16:26:05 Semiconductor companies Digital electronics Instruction set architectures Mitsui NEC Intel Central processing unit V30 DEC Alpha Electronic engineering Computer hardware Computer architecture
248	APPLICATION NOTE Atmel AVR2031: ATRF231USB-RD – Quick Start Guide 8-bit Atmel Microcontrollers Features • Add to Reading List Source URL: www.atmel.com Language: English - Date: 2014-10-13 03:47:53 Computer architecture Instruction set architectures Atmel AVR Norwegian Institute of Technology Embedded systems Atmel Joint Test Action Group Universal Serial Bus Booting Microcontrollers Electronics Computer hardware
249	The University of Hertfordshire The Challenges facing Libraries and Imperative Languages from Massively Parallel Architectures Jason McGuiness Add to Reading List Source URL: accu.org Language: English - Date: 2008-04-14 03:49:41 Central processing unit Parallel computing Classes of computers Microprocessors Instruction-level parallelism Superscalar Very long instruction word CPU cache Instruction set Computer architecture Computing Computer hardware
250	Microsoft Word - FastKVS_Final.docx Add to Reading List Source URL: www.aerospike.com Language: English - Date: 2015-02-09 14:14:14 Computer memory Instruction set architectures Intel Xeon Solid-state drive X86 Random-access memory Multi-core processor Computing Computer hardware Computer architecture

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